1. Field of the Invention
The present invention relates to an inspection condition setting programs that are executed by inspection devices or inspection systems for products such as semiconductor integrated circuits.
2. Description of the Related Art
The related art is described below using manufacture of semiconductor integrated circuits as an example. The manufacturing processes for integrated circuits are typically divided into wafer patterning processes and packaging processes. In wafer patterning processes, chips are manufactured with formation of multiple layers, such as circuit and interconnection pattern layers, usually on a silicon wafer. In packaging processes, the chips are separated and packaged.
In the wafer pattering processes, disconnections or short-circuits of the circuit patterns may arise because of such defects as particles or deformed patterns generated during manufacture. Un-patterned or patterned wafer inspection devices are employed to monitor defects. An un-patterned wafer inspection device directs a laser beam onto the wafer in inclined fashion from above and the scattered light is detected. The device is sometimes referred to as a “dark field” inspection device. A patterned wafer inspection device detects abnormal locations by picking up images of the circuit patterns and performing image processing thereon. Patterned wafer inspection devices are categorized into “bright field” inspection devices or SEM (Scanning Electron Microscope) inspection devices depending on the detector employed. The article “Inspection System Supporting Improved Semiconductor Yields” in the October 1999 issue of the Hitachi Journal describes these devices. However, there is no clear distinction between the un-patterned and patterned wafer inspection devices except the principle of inspection. In the present application, both devices are referred to generally as defect inspection devices.
Defect inspection devices play an important role in high-sensitivity detection of defects on circuit patterns formed on wafers. To make full use of the defect inspection device, it is necessary to set suitable inspection conditions in accordance with the method of deposition onto the wafer and the method of formation of the circuit patterns. Typically, a defect inspection device requires inspection conditions set beforehand to execute inspection programs. Two of the conditions to be set are circuit pattern conditions and optical/image processing conditions.
The circuit pattern conditions include parameters such as the size of the chips that are formed on the wafer, the arrangement information and region information within the inspection algorithm can be changed accordingly. In addition, the optical/image processing conditions determine the inspection sensitivity and include parameters such as the amount of laser illumination that depends on deposition conditions and the wiring material, the contrast condition of images picked up by the detectors, and threshold values in image processing etc. The circuit pattern conditions and optical/image processing conditions are interrelated.
In the circuit pattern conditions, parameters such as size and arrangement of the chips formed on the wafer are the same parameters used in exposure conditions. Since the inspection algorithms can be changed depending on the circuit pattern of the integrated circuit, regions within a chip need to be set for executing the respective algorithms. The inspection algorithms include, for example, chip comparison methods (also called die comparison methods), cell comparison methods and mixed comparisons methods combining chip comparison and cell comparison. Japanese Patent No. 3187827 discloses these methods. Note that in some cases detection sensitivity can be increased by excluding some regions from the defect inspection area. The regions to be excluded are, for example, a region in which no circuit pattern is present, such as the region between one chip and another on the wafer (called the “scribe lines”), or the region between one circuit block and another in a chip. In setting the circuit pattern conditions, such regions are registered as non-inspection regions.
Conventionally, circuit pattern conditions, except the parameters of the size and the arrangement of chips on the wafer, must be determined while observing the surface of the real wafer. To observe the surface of the real wafer, the wafer must be set into the defect inspection device and moved with an XY stage that holds the wafer.